Due to the extensive use and broad range of applications of integrated circuits a wide variety of semiconductor memory devices have been developed. These semiconductor memory devices are continuously being applied to new and expanding uses, which in turn require an integrated circuit of increased capabilities and decreased cost. Accordingly, there exists a continuing demand for inexpensive semiconductor devices having increased memory and reduced chip size. Improvements of this nature have been realized in device miniaturization and improved layout and design of semiconductor memory devices.
Many prior art devices utilize recessed oxide (ROX) isolation trenches to separate adjacent trench capacitor cells as a means for preventing electrical interferences (i.e. due to leakage from the channel region of the adjacent memory cell) and parasitic device formation between the trench capacitor and the edge of an active semiconductor region abuting the trench capacitor. Accordingly, when utilizing designs or structures incorporating the ROX isolation trenches, there is a minimum distance (the length of the ROX trench) which must be maintained between the memory cell capacitor and gate electrode of adjacent memory cells in order to avoid electrical interferences and parasitic device formation between the two components. However, the semiconductor substrate area occupied by the ROX isolation trenches is considerable. Thus, a semiconductor device design which avoids or minimizes the use of ROX isolation trenches allows a more densely packed memory array and is, therefore, preferred.
In addition, many memory devices, such as DRAM cells, utilize a dynamic memory cell wherein a bit is represented by a charge stored in a capacitor structure. In DRAM cells the capacitor structure must be coupled with the storage node of the FET. However, due to the already high density of existing semiconductor devices little room is available for surface straps. Moreover, due to the high device density and minimum feature size it is necessary for processing sequences to be compatible with an ever increasing range of structures and materials. For example, contacts are generally formed by etching contact holes in a passivation layer over the areas where the contacts are to be made, followed by depositing a conductive material therein. However, due to the topology of the semiconductor device, formation of the contact holes may often cause damage to other surface structures, such as gate conductors (word lines), or to the passivation layers themselves. It is, therefore, often preferred to provide a buried strap for connecting various regions of the semiconductor device. First, since the strap is buried it leaves more room on the surface of the semiconductor device and, thus, facilitates realization of even higher device densities. Secondly, since the strap contacts are formed at the front end of the integrated process (i.e. prior to formation of many structures) potential damage to other surface structures is obviated.
There exists a continuing demand for semiconductor memory device designs and processes which utilize fewer processing sequences, while at the same time facilitating greater storage capacity and allowing more densely packed memory arrays. There further exists a need for a trench capacitor structure having a buried strap and isolation structure, both of which are aligned with the trench capacitor structure.